The present invention describes a method and apparatus by which interrupts may be eliminated in a pipelined computer system using a communication system and a polling system to efficiently utilize computer time and memory usage.
Modern microprocessor instruction execution involves the use of a series of discrete stages called a xe2x80x9cpipeline xe2x80x9d to break problems into logically organized pieces. By executing processes on a pipeline, the processor (e.g., a xe2x80x9cCPU xe2x80x9d) can work on several different problems at once, thus greatly increasing the rate of process completion.
In prior art systems, input/output (xe2x80x9cI/O xe2x80x9d) requests are not processed in the normal CPU pipeline system. Instead, pending I/O processes obtain the attention of the CPU by signaling an interrupt, which causes the CPU to stop whatever process it is currently executing in order to address the needs of the pending I/O process. When an interrupt is signaled, a xe2x80x9ccontext switch xe2x80x9d is triggered which forces the CPU to save its current status to registers and non-local memory before processing the pending I/O request. After the CPU processes the pending I/O request, the status of the CPU that existed prior to the interrupt is retrieved from the registers and non-local memory and the CPU resumes processing using the normal pipeline system. These context switches result in a significant amount of execution time loss because they force the CPU to spend time in memory access and force the operating system (xe2x80x9cOS xe2x80x9d) to reschedule other active processes to make room for I/O completion processing. Furthermore, typical I/O completion processing uses slow, non-cacheable memory-mapped registers located on I/O adapters across an I/O expansion bus, thus loading the system and I/O buses with further overhead.
Consequently, there is a need in the art for a method and apparatus of I/O process completion that does not require an interruption in the normal activities of the OS, the processor pipeline, or the system and I/O buses.
Embodiments of the present invention provide for an apparatus for input/output processing that includes a plurality of descriptors where each descriptor includes a completion indicator and data associated with an input/output request. The plurality of descriptors includes a head descriptor and a tail descriptor. Embodiments of the present invention further include a plurality of address holders associated with an input/output processor, and each the plurality of address holders is uniquely affiliated with one of the plurality of descriptors. Embodiments of the present invention further include a polling mechanism for evaluating the completion indicator of the head descriptor and a completion processor for interfacing with the head descriptor. Finally, embodiments of the present invention include connectors between the tail descriptor and address holder and between the input/output processor and the head descriptor.